%FILENAME%
verilator-4.220-1-x86_64.pkg.tar.zst

%NAME%
verilator

%BASE%
verilator

%VERSION%
4.220-1

%DESC%
The fastest free Verilog HDL simulator

%CSIZE%
4706945

%ISIZE%
22110861

%MD5SUM%
139d84d3e4a492f09de2a7a18c5fcde9

%SHA256SUM%
167ec7a90992cfdb8e6e0ea831c379c0fe2e40997d99012a29b644c54bacb713

%PGPSIG%
iQJIBAABCAAyFiEE6HyevZCe8oInuRJWULwdtYO3lwYFAmNhOpgUHGFzbWVyb25AdWJsaW51eC5jb20ACgkQULwdtYO3lwYbmg//c45ePqLtJK5eZW1dD+bE7apxfJ4LEKJz6Y4JQbTUOthOAq9cOVVE0KTbkLGu1dR1wpTtTgFoat7zjEwRPF6RjjbWTn9ocPHdQuHmJkQUEBcelzxbVt8hXRc+/t9z/DKxOYpcQwceGRkqfGG0ongvjqDP41yMsQy61uxOfbVCbQR3ZNuUR7XzDNsimzeS8rE7tB3jt9Gts7Qsh8Qwm9lmYxr52+ejOTkwGYPnXyLqcI/ydOjrW3TBAhImd5EZfz2i45a13ox33Fnfngj3hefXCctG5SfURYByEyVPRB2JjvfcfX9TfPqKEZiVdylbuwf146t8WQYT7Wg/sHOv0F5zxa06+CJl1SPXjDmE6iPaGDwhumVnKICvJ+hPsDSdbJnenBLreot/kJWxaojZZ1/68HntJDg2Ug0gt9aEezYoZQWdCDoRuHJhBfEBYJe/bv8R0q+1a0SXAtlm47pOnTGh3In2P5Oa7zH9Tjgje1ZyMaG0qsxgQb6oWY7c/G7BtmKIT+IgfaNaYWb5glH/NE2vI6LzHjv4V42Z0n59fLxOMn8w6AanRSp13kix/O4Sq1eYB1ne60+/2hRcEUtQVpx/mCzSDmEaz/Q3MYRYrc3CRe4LQsHlgH18B1ONVv7x0Xge3SiXtTuLDKrZuX1tEMLkvkZELXDa/jT0n/zKxkLQJxY=

%URL%
https://www.veripool.org/projects/verilator/wiki/Intro

%LICENSE%
LGPL

%ARCH%
x86_64

%BUILDDATE%
1647204701

%PACKAGER%
Felix Yan <felixonmars@archlinux.org>

%DEPENDS%
perl

%OPTDEPENDS%
systemc

%MAKEDEPENDS%
python
systemc

